<html>
<head><meta charset="utf-8"><title>packed_simd vector types · project-inline-asm · Zulip Chat Archive</title></head>
<h2>Stream: <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/index.html">project-inline-asm</a></h2>
<h3>Topic: <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html">packed_simd vector types</a></h3>

<hr>

<base href="https://rust-lang.zulipchat.com">

<head><link href="https://rust-lang.github.io/zulip_archive/style.css" rel="stylesheet"></head>

<a name="208029146"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208029146" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208029146">(Aug 25 2020 at 21:55)</a>:</h4>
<p>What would it take to make packed_simd vector types usable with zmm registers in the new asm?</p>



<a name="208029493"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208029493" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208029493">(Aug 25 2020 at 21:58)</a>:</h4>
<p>They need to use <code>#[repr(simd)]</code> and match one of the native SIMD types for the target.</p>



<a name="208030577"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208030577" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208030577">(Aug 25 2020 at 22:08)</a>:</h4>
<p>Is there another crate that is usable now? It's hard to tell what crates are current.</p>



<a name="208031612"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208031612" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208031612">(Aug 25 2020 at 22:21)</a>:</h4>
<p>Ah, it looks like they (packed_simd types) already repr(simd) (e.g. <a href="https://github.com/rust-lang/packed_simd/blob/master/src/codegen.rs#L15">https://github.com/rust-lang/packed_simd/blob/master/src/codegen.rs#L15</a>) , but they definitely don't work for me, I get a message saying "only integers, floats, SIMD vectors, pointers and function pointers can be used as arguments for inline assembly"</p>



<a name="208037173"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208037173" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208037173">(Aug 25 2020 at 23:31)</a>:</h4>
<p><span class="user-mention" data-user-id="143274">@Amanieu</span>  are there any examples you know of that use SIMD (with any crate) with the new asm! ? I just went and surveyed the simd crates landscape again, and it looks like packed_simd is maybe the main one in use right now in the ecosystem. If it doesn't work, what does?</p>



<a name="208037194"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208037194" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208037194">(Aug 25 2020 at 23:31)</a>:</h4>
<p>You can use the SIMD types from <code>std::arch</code> like <code>__m128</code>.</p>



<a name="208037377"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208037377" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208037377">(Aug 25 2020 at 23:34)</a>:</h4>
<p>Ah, I see. I'll try that, thanks.</p>



<a name="208038996"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208038996" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208038996">(Aug 25 2020 at 23:57)</a>:</h4>
<p><span class="user-mention" data-user-id="143274">@Amanieu</span> sorry if I'm being dense, but how do I even instantiate one of those? I need an __m512i. If I do it like __m512i(0,0,0,0,0,0,0,0) it says it expected a function call, and hints that I should use the explicit struct syntax. If I use the explicit struct syntax: __m512i { 0: 0, 1: 0, 2: 0, 3: 0, 4: 0, 5:0, 6:0, 7:0}, it says all the fields are private.</p>



<a name="208041346"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208041346" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Lokathor <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208041346">(Aug 26 2020 at 00:32)</a>:</h4>
<p>you can transmute an array of appropriate size and type into the register type. Also you can call an appropriate intrinsic.</p>



<a name="208107854"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208107854" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208107854">(Aug 26 2020 at 15:30)</a>:</h4>
<p>Thanks <span class="user-mention" data-user-id="224471">@Lokathor</span>  and <span class="user-mention" data-user-id="143274">@Amanieu</span>  that helped. Now it compiles, yay! But when it runs, I get illegal hardware instruction. My asm is only one instruction, so I know which one it is, but I can't see what I did wrong. Here's the function, can anyone tell what I'm doing wrong?</p>
<div class="codehilite"><pre><span></span><code>const ONES_64: __m512i = unsafe { std::mem::transmute([1u8; 64]) };

unpack_u64(packed: u64) -&gt; u8x64 {
  unsafe {
      let mut block :__m512i  = core::mem::zeroed();

      asm! {
          &quot;vpexpandb {unpacked}{{ {mask} }}{{z}}, {packed}&quot;,
          packed = in(zmm_reg) ONES_64,
          mask = in(kreg) packed,
          unpacked = out(zmm_reg) block,
      }
      std::mem::transmute(block)
  }
}
</code></pre></div>


<p>I've also tried actually initializing <code>block</code> to zeros in the same way I did the const, and I've tried returning a dummy value instead of transmuting <code>block</code> at the end, so the problem is definitely in the vpexpand call, and gdb also confirms.</p>



<a name="208108764"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208108764" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> bjorn3 <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208108764">(Aug 26 2020 at 15:38)</a>:</h4>
<div class="codehilite"><pre><span></span><code>vpexpandb zmm2{ k0 }{z}, zmm1
</code></pre></div>


<p>gives an assembler error for me.</p>



<a name="208109078"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208109078" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208109078">(Aug 26 2020 at 15:40)</a>:</h4>
<p>But rustc was happy? This is an avx512f instruction, maybe your cpu doesn't support it?</p>



<a name="208109784"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208109784" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Lokathor <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208109784">(Aug 26 2020 at 15:46)</a>:</h4>
<p>MaybeUninit and then immediately assuming it's init is exactly how you should not use the type. it's instant UB</p>



<a name="208109864"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208109864" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208109864">(Aug 26 2020 at 15:47)</a>:</h4>
<p>How should it be done instead? The examples in MaybeUninit docs aren't clear for this kind of case.</p>



<a name="208109967"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208109967" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208109967">(Aug 26 2020 at 15:48)</a>:</h4>
<p>Also, I tried initializing it instead of using MaybeUninit, the illegal hardware instruction error still happens</p>



<a name="208110311"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208110311" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Lokathor <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208110311">(Aug 26 2020 at 15:51)</a>:</h4>
<p>MaybeUninit should essentially never be used unless you're a super pro at rust. It's that easy to get wrong.</p>
<p>Use <code>core::mem::zeroed()</code> instead</p>



<a name="208110402"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208110402" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208110402">(Aug 26 2020 at 15:52)</a>:</h4>
<p>OK, thanks.</p>



<a name="208110738"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208110738" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208110738">(Aug 26 2020 at 15:54)</a>:</h4>
<p>I've updated the example to use core::mem::zeroed as you suggested. The illegal hardware instruction still happens.</p>



<a name="208110868"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208110868" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208110868">(Aug 26 2020 at 15:55)</a>:</h4>
<p>Use a debugger, it's probably your CPU not supporting AVX512</p>



<a name="208110996"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208110996" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208110996">(Aug 26 2020 at 15:56)</a>:</h4>
<p>I have CPUs where it's not supported, it doesn't compile there. On this machine, I have AVX512 and it compiles.</p>



<a name="208111107"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208111107" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208111107">(Aug 26 2020 at 15:57)</a>:</h4>
<p>Flags:                 fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch epb cat_l3 cdp_l3 invpcid_single intel_pt spec_ctrl ibpb_support tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm mpx rdt_a avx512f avx512dq rdseed adx smap clflushopt clwb avx512cd avx512bw avx512vl xsaveopt xsavec xgetbv1 cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req</p>



<a name="208111646"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208111646" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208111646">(Aug 26 2020 at 16:01)</a>:</h4>
<p>Program received signal SIGILL, Illegal instruction.<br>
[Switching to Thread 0x7ffd56bf5700 (LWP 21181)]<br>
0x00007fffdd74b2a8 in unpack_u64 (packed=&lt;optimized out&gt;) at src/posh.rs:95<br>
95              asm! {</p>



<a name="208112209"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208112209" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208112209">(Aug 26 2020 at 16:06)</a>:</h4>
<p>So I have avx512 in all its glory, but this is still an illegal instruction somehow. What does that mean?</p>



<a name="208112296"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208112296" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208112296">(Aug 26 2020 at 16:06)</a>:</h4>
<p><code>disas</code></p>



<a name="208112301"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208112301" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208112301">(Aug 26 2020 at 16:07)</a>:</h4>
<p>in gdb</p>



<a name="208112548"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208112548" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208112548">(Aug 26 2020 at 16:09)</a>:</h4>
<p>To show the instruction it's crashing on</p>



<a name="208112741"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208112741" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208112741">(Aug 26 2020 at 16:10)</a>:</h4>
<p>0x00007fffdd74b2a8 &lt;+312&gt;:   (bad)  {%k1}{z}</p>



<a name="208112880"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208112880" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208112880">(Aug 26 2020 at 16:12)</a>:</h4>
<p>I don't know what could be causing that...</p>



<a name="208112934"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208112934" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208112934">(Aug 26 2020 at 16:12)</a>:</h4>
<p>Could be a bug in LLVM's assembler.</p>



<a name="208112978"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208112978" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208112978">(Aug 26 2020 at 16:12)</a>:</h4>
<p>OK</p>



<a name="208113003"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208113003" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208113003">(Aug 26 2020 at 16:12)</a>:</h4>
<p><a href="https://rust.godbolt.org/z/7WM8ad">This</a> seems to generate a valid instruction</p>



<a name="208113247"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208113247" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208113247">(Aug 26 2020 at 16:15)</a>:</h4>
<p>Yes, and the code in --emit asm looks similar, though it's inlined into other functions</p>



<a name="208113535"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208113535" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208113535">(Aug 26 2020 at 16:17)</a>:</h4>
<p>It seems that vpexpandb is part of AVX512-VBMI2 which your cpu doesn't support.</p>



<a name="208113559"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208113559" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208113559">(Aug 26 2020 at 16:17)</a>:</h4>
<p>It's not part of the base AVX512 ISA.</p>



<a name="208114027"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208114027" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208114027">(Aug 26 2020 at 16:20)</a>:</h4>
<p>Arggh! Thanks so much for helping me track this down.</p>



<a name="208114245"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208114245" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208114245">(Aug 26 2020 at 16:22)</a>:</h4>
<p>Oh wait, according to the manual it's in AVX512VL as well, which I do have</p>



<a name="208114314"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208114314" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208114314">(Aug 26 2020 at 16:22)</a>:</h4>
<p>Oh wait again, most of them are, but not this specific variant. Sigh</p>



<a name="208114334"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208114334" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208114334">(Aug 26 2020 at 16:23)</a>:</h4>
<p>No, the manual says it requires <em>both</em> VL and VBMI</p>



<a name="208114525"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/packed_simd%20vector%20types/near/208114525" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Bryn Keller <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/packed_simd.20vector.20types.html#208114525">(Aug 26 2020 at 16:24)</a>:</h4>
<p>Ah. Oh well. Thanks again for all your help!</p>



<hr><p>Last updated: Aug 07 2021 at 22:04 UTC</p>
</html>